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artiq_experiments
Commit 7e2c6b91 authored by Nicolas Nunez Barreto's avatar Nicolas Nunez Barreto
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Urukul ahora anda para modAM

parent cd346c12
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Showing with 58 additions and 70 deletions
artiq_master/repository/Experiments/Spectrum/With_calibration/Motional/urukul_RAM_AM.py
View file @ 7e2c6b91
......@@ -91,29 +91,41 @@ def convert_amp_to_data(amp):
class AD9910RAM(EnvExperiment):
'''Amplitude Modulation for Ch3'''
'''Amplitude Modulation (for any channel)'''
def build(self): #this code runs on the host computer
self.setattr_device("core") #sets core device drivers as attributes
self.u = self.get_device("urukul0_ch3") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u
self.u = [ self.get_device("urukul0_ch0"),
self.get_device("urukul0_ch1"),
self.get_device("urukul0_ch2"),
self.get_device("urukul0_ch3")]
# self.data=[0]*512 + [1000<<23]*512
self.data = [0]*1024
self.data_len = 1024
# GUI
self._channel_list = list( [ f'Ch{jj}' for jj in range(4) ] )
self.setattr_argument("channel",EnumerationValue(self._channel_list))
self.frequency = self.get_argument(f"frequency",NumberValue(50*MHz, unit='MHz', scale=MHz, min=1*MHz, max=400*MHz),'ch3')
self.amplitude = self.get_argument(f"amplitude",NumberValue( 1, min=0.000, max=1.000),'ch3')
self.depth = self.get_argument(f"AM Depth", NumberValue( 0.1, min=0.000, max=1.000),'ch3')
self.am_freq = self.get_argument(f"AM frequency",NumberValue(100*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz),'ch3')
self.frequency = self.get_argument(f"frequency",NumberValue(100*MHz, unit='MHz', scale=MHz, min=1*MHz, max=400*MHz))
self.amplitude = self.get_argument(f"amplitude",NumberValue( 0.25, min=0.000, max=1.000))
self.depth = self.get_argument(f"AM Depth", NumberValue( 0.15, min=0.000, max=1.000))
self.am_freq = self.get_argument(f"AM frequency",NumberValue(700*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz))
self._channel = 0
def run(self):
# print(self.am_freq)
# for am_delta in range(1000,5000,1000):
# parameters = get_urukul_params( self.am_freq + am_delta )
self._channel = self._channel_list.index( self.channel )
print("canal:", self._channel)
# assert self._channel==3
parameters = get_urukul_params( self.am_freq )
frec, num_samples, clock_step, n_harmonic = parameters
modulation = get_urukul_array(frec, num_samples, n_harmonic)
......@@ -121,24 +133,47 @@ class AD9910RAM(EnvExperiment):
data = convert_amp_to_data( modulation )
self.clock_step = clock_step
self.data_len = len(data)
self.data_len = int(num_samples)
# entre 865 y 870
# self.data_len = 871
for ii in range(self.data_len):
self.fix = False
# if (870 <= self.data_len <= 880) or self.data_len == 908:
# data = data + [0]*10
# self.fix = True
for ii in range(len(data)):
self.data[ii] = data[ii]
# print(self.data)
print(f"frec: {frec} | am_freq: {self.am_freq} | num_samples:{num_samples} | clock_step: {clock_step}")
self.run_kernel()
try:
self.run_kernel()
except:
print("HUBO UNA FALLA DEL run_kernel()")
self.fix = True
data = data + [0]*10
for ii in range(len(data)):
self.data[ii] = data[ii]
self.run_kernel()
@kernel #this code runs on the FPGA
def run_kernel(self):
data = [0] * self.data_len
for ii in range(self.data_len):
if self.fix:
local_data_len = self.data_len + 10
else:
local_data_len = self.data_len
data = [0] * local_data_len
for ii in range(local_data_len):
data[ii] = self.data[ii] << 23
self.core.break_realtime()
......@@ -153,67 +188,20 @@ class AD9910RAM(EnvExperiment):
self.core.reset()
#initialise
self.u.cpld.init()
self.u.init()
self.u[self._channel].cpld.init()
self.u[self._channel].init()
delay(1*ms)
#set ram profile 0 -----------------------------
self.u.set_profile_ram(
start=0, end=0 + len(data) - 1, step=self.clock_step,
self.u[self._channel].set_profile_ram(
start=0, end=0 + self.data_len - 1, step=self.clock_step,
profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8)
self.u[self._channel].cpld.set_profile(0)
self.u[self._channel].cpld.io_update.pulse_mu(8)
delay(1*ms) # ES ESTE
#write to ram
self.u.write_ram(data)
#
#
# if self.data_len>100:
# self.u.set_profile_ram(
# start=0, end=0 + len(data[:100]) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms) # ES ESTE
# #write to ram
# self.u.write_ram(data[:100])
#
# delay(1*ms)
#
# self.u.set_profile_ram(
# start=len(data[:100]), end=len(data[:100]) + len(data[100:]) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms) # ES ESTE
# #write to ram
# self.u.write_ram(data[100:])
#
# delay(1*ms)
# self.u.set_profile_ram(
# start=0, end=0 + len(data[:100]) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
#
# else:
# self.u.set_profile_ram(
# start=0, end=0 + len(data) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms) # ES ESTE
# #write to ram
# self.u.write_ram(data)
self.u[self._channel].write_ram(data)
delay(10*ms)
......@@ -228,12 +216,12 @@ class AD9910RAM(EnvExperiment):
#write to cfr
self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF, internal_profile=0)
self.u[self._channel].set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF, internal_profile=0)
self.u.sw.on()
self.u[self._channel].sw.on()
#set urukuln parameters and turn channel on
self.u.set_frequency(self.frequency)
self.u.cpld.io_update.pulse_mu(8)
self.u[self._channel].set_frequency(self.frequency)
self.u[self._channel].cpld.io_update.pulse_mu(8)
# self.u.set_att(10*dB)
# self.core.break_realtime()
......
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