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Commit d0b09909 authored by Nicolas Nunez Barreto's avatar Nicolas Nunez Barreto
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agrego todos los acrhivios

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artiq_master/repository/Examples/Amplitude_Modulation/ram_test_2.py deleted 100644 → 0
View file @ abfeb9c8
from artiq.experiment import * #Imports everything from experiment library
from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source
RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP)
#This code demonstrates use of the urukul RAM. It produces a 125MHz pulse that ramps up in amplitude, holds a fixed amplitude and then ramps back down
class AD9910RAM(EnvExperiment):
# '''Urukul RAM Amplitude Ramp TESTINET'''
# def build(self): #this code runs on the host computer
# self.setattr_device("core") #sets core device drivers as attributes
# self.u = self.get_device("urukul0_ch1") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u
@kernel #this code runs on the FPGA
def run(self):
#produce data to be loaded to RAM
n = 10 #defines variable n for list length exponent
data = [0]*(1 << n) #declares list as 2^n integer values
for i in range(len(data)//2): #splits list into 2 halves and defines each separately
data[i] = i << (32 - (n - 1)) #first half ramps up to maximum amplitude in machine units
data[i + len(data)//2] = 0xffff << 16 #second half holds maximum amplitude
#reset core
self.core.reset() #resets core device
#initialise
self.u.cpld.init() #initialises CPLD
self.u.init() #initialises urukul channel
delay(1*ms) #1ms delay
#set ram profile
self.u.set_profile_ram( #sets profile in RAM to be used
start=0, end=0 + len(data) - 1, step=250, #start/end give addresses of ends of ram data, step gives step length
profile=0, mode=RAM_MODE_CONT_RAMPUP) #mode: bidirectional ramp
self.u.cpld.set_profile(0) #sets CPLD profile pins
self.u.cpld.io_update.pulse_mu(8) #I think this clocks all the CPLD registers so they take the values written to them
delay(1*ms) #1ms delay
#write to ram
self.u.write_ram(data) #writes data list to ram
delay(10*ms) #10ms delay
#write to cfr
self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF) #writes to CFR1 (control function register 1)
#enables ram, sets ram data as amplitude scale factor
self.u.sw.on()
#set urukuln parameters and turn channel on
self.u.set_frequency(5*MHz) #sets frequency
self.u.cpld.io_update.pulse_mu(8) #I think this clocks all the CPLD registers so they take the values written to them
# self.u.set_att(10*dB) #sets attenuation
#turns urukul channel on
# self.core.break_realtime() #moves timestamp forward to prevent underflow
delay(1*ms) #this can alse be achieved with a fixed delay
#self.u.sw.off() #this can alse be achieved with a fixed delay
# while True: #loops until manually broken
# delay(1*ms) #1ms delay
#
# with parallel: #runs indented code in parallel
# self.u.cpld.set_profile(0) #profile 0 tells CPLD to start ramping up
#
# delay(2*us) #2us delay
#
# with parallel: #runs indented code in parallel
# self.u.cpld.set_profile(1) #profile 1 tells CPLD to start ramping back down
artiq_master/repository/Examples/Amplitude_Modulation/urukul_DDS_block_RAM.py deleted 100644 → 0
View file @ abfeb9c8
from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP
from artiq.coredevice.ad9910 import RAM_DEST_ASF
from artiq.experiment import* #imports everything from the artiq experiment library
class Urukul_Frequency_RAM(EnvExperiment):
# """Urukul Frequency RAM lolo"""
#
# def build(self): #This code runs on the host device
# self.setattr_device("core") #sets core device drivers as attributes
# self.setattr_device("urukul0_ch1") #sets urukul0, channel 1 device drivers as attributes
# self.prepare()
@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
self.urukul0_ch1.cpld.init()
self.urukul0_ch1.cpld.io_rst()
# self.init_dds(self.dds0)
# self.core.break_realtime()
self.urukul0_ch1.init()
# self.urukul0_ch1.set_att(6.*dB)
self.urukul0_ch1.cfg_sw(True)
self.configure_ram_mode(self.urukul0_ch1)
def prepare(self):
print("Runing prepare")
self.amp = [0.7, 0.7, 1.0, 0.7, 0.0, 0.0, 0.0] # Reversed Order
self.asf_ram = [0] * len(self.amp)
@kernel
def configure_ram_mode(self, dds):
self.core.break_realtime()
dds.set_cfr1(ram_enable=0)
dds.cpld.io_update.pulse_mu(8)
delay(1*ms)
dds.cpld.set_profile(0) # Enable the corresponding RAM profile
# Profile 0 is the default
dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
# El step de esa función son pasos en unidades de t_DDS (tipico 4 ns). Es un int32.
# https://github.com/m-labs/artiq/blob/master/artiq/coredevice/ad9910.py#L616
dds.cpld.io_update.pulse_mu(8)
delay(1*ms)
dds.amplitude_to_ram(self.amp, self.asf_ram)
dds.write_ram(self.asf_ram)
delay(10*ms)
self.core.break_realtime()
dds.set(frequency=5*MHz)
# # Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
# # Acá le dijiste que el destino de la RAM es la amplitud (ASF)
# # el CFR1 es un registro del ad9910. Ver pag 49 de AD9910.pdf
dds.cpld.io_update.pulse_mu(8)
delay(1*ms)
# print(self.asf_ram)
artiq_master/repository/Examples/Amplitude_Modulation/urukul_DDS_block_RAM_inet_example.py deleted 100755 → 0
View file @ abfeb9c8
from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP
from artiq.experiment import* #imports everything from the artiq experiment library
def build(self): #This code runs on the host device
self.setattr_device("core") #sets core device drivers as attributes
self.setattr_device("urukul0_ch1") #sets urukul0, channel 1 device drivers as attributes
def prepare(self):
self.amp = [0.0, 0.0, 0.0, 0.7, 0.0, 0.7, 0.7] # Reversed Order
self.asf_ram = [0] * len(self.amp)
@kernel
def init_dds(self, dds):
self.core.break_realtime()
dds.init()
# dds.set_att(1.0)
dds.cfg_sw(True)
@kernel
def configure_ram_mode(self, dds):
self.core.break_realtime()
dds.set_cfr1(ram_enable=0)
self.cpld.io_update.pulse_mu(8)
self.cpld.set_profile(0) # Enable the corresponding RAM profile
# Profile 0 is the default
dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
# El step de esa función son pasos en unidades de t_DDS (tipico 4 ns). Es un int32.
# https://github.com/m-labs/artiq/blob/master/artiq/coredevice/ad9910.py#L616
self.cpld.io_update.pulse_mu(8)
dds.amplitude_to_ram(self.amp, self.asf_ram)
dds.write_ram(self.asf_ram)
self.core.break_realtime()
dds.set(frequency=5*MHz, ram_destination=RAM_DEST_ASF)
# Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
# Acá le dijiste que el destino de la RAM es la amplitud (ASF)
# el CFR1 es un redistro del ad9910. Ver pag 49 de AD9910.pdf
self.cpld.io_update.pulse_mu(8)
@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
self.cpld.init()
self.init_dds(self.dds0)
self.configure_ram_mode(self.dds0)
artiq_master/repository/Examples/Amplitude_Modulation/urukul_DDS_block_RAM_test.py deleted 100644 → 0
View file @ abfeb9c8
from artiq.coredevice.ad9910 import RAM_MODE_CONT_RAMPUP
from artiq.coredevice.ad9910 import RAM_DEST_ASF
from artiq.experiment import* #imports everything from the artiq experiment library
class Urukul_Frequency_RAM(EnvExperiment):
# """Urukul Frequency RAM lolo TEST"""
#
# def build(self): #This code runs on the host device
# self.setattr_device("core") #sets core device drivers as attributes
# self.setattr_device("urukul0_ch1") #sets urukul0, channel 1 device drivers as attributes
# self.prepare()
@kernel
def run(self):
self.core.reset()
self.core.break_realtime()
self.urukul0_ch1.cpld.init()
self.urukul0_ch1.cpld.io_rst()
# self.init_dds(self.dds0)
# self.core.break_realtime()
self.urukul0_ch1.init()
# self.urukul0_ch1.set_att(6.*dB)
self.urukul0_ch1.cfg_sw(True)
self.urukul0_ch1.set(frequency=5*MHz)
# print(str(dir(self.urukul0_ch1)))
self.configure_ram_mode(self.urukul0_ch1)
def prepare(self):
print("Runing prepare")
self.amp = [0.7, 0.7, 1.0, 0.7, 0.0, 0.0, 0.0] # Reversed Order
self.asf_ram = [0] * len(self.amp)
@kernel
def configure_ram_mode(self, dds):
self.core.break_realtime()
dds.set_cfr1(ram_enable=0)
dds.cpld.io_update.pulse_mu(8)
delay(1*ms)
dds.cpld.set_profile(0) # Enable the corresponding RAM profile
# Profile 0 is the default
dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
# El step de esa función son pasos en unidades de t_DDS (tipico 4 ns). Es un int32.
# https://github.com/m-labs/artiq/blob/master/artiq/coredevice/ad9910.py#L616
dds.cpld.io_update.pulse_mu(8)
delay(1*ms)
dds.amplitude_to_ram(self.amp, self.asf_ram)
dds.write_ram(self.asf_ram)
delay(10*ms)
self.core.break_realtime()
# dds.set(frequency=5*MHz)
# dds.set_profile_ram(start=0, end=len(self.asf_ram)-1,step=250, profile=0, mode=RAM_MODE_CONT_RAMPUP)
# lolo = []
# dds.read_ram(lolo)
# # Pass osk_enable=1 to set_cfr1() if it is not an amplitude RAM
dds.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
# # Acá le dijiste que el destino de la RAM es la amplitud (ASF)
# # el CFR1 es un registro del ad9910. Ver pag 49 de AD9910.pdf
dds.cpld.io_update.pulse_mu(8)
delay(1*ms)
# print(self.asf_ram)
artiq_master/repository/Examples/Amplitude_Modulation/urukul_DDS_simple.py deleted 100755 → 0
View file @ abfeb9c8
from artiq.experiment import* #imports everything from the artiq experiment library
import numpy as np
#This code outputs a predefined frequency at a fixed amplitude on a single channel of the urukul
#The ouput persists for 2 seconds and the turns off
class Urukul_Frequency_Pulse(EnvExperiment):
"""Urukul Single Frequency Pulse DDS Simple"""
def build(self): #This code runs on the host device
self.setattr_device("core") #sets core device drivers as attributes
self.setattr_device("urukul0_ch1") #sets urukul0, channel 1 device drivers as attributes
@kernel #This code runs on the FPGA
def run(self):
self.core.reset() #resets core device
self.urukul0_ch1.cpld.init() #initialises CPLD on channel 1
self.urukul0_ch1.init() #initialises channel 1
delay(10 * ms) #10ms delay
freq = 5*MHz #defines frequency variable
amp = 1.0 #defines amplitude variable as an amplitude scale factor(0 to 1)
attenuation= 1.0 #defines attenuation variable
self.urukul0_ch1.set_att(attenuation) #writes attenuation to urukul channel
self.urukul0_ch1.sw.on() #switches urukul channel on
self.urukul0_ch1.set(freq, amplitude = amp) #writes frequency and amplitude variables to urukul channel thus outputting function
delay(1*us) #2s delay
# self.urukul0_ch1.sw.off() #switches urukul channel off
for val in [ a/10 for a in range(10)]:
self.urukul0_ch1.set(freq,amplitude = val )
delay(1*us)
self.urukul0_ch1.sw.off()
artiq_master/repository/Examples/Amplitude_Modulation/urukul_DDS_simple_sine_not_mod.py deleted 100644 → 0
View file @ abfeb9c8
from artiq.experiment import* #imports everything from the artiq experiment library
#This code outputs a predefined frequency at a fixed amplitude on a single channel of the urukul
#The ouput persists for 2 seconds and the turns off
class Urukul_Frequency_ch1(EnvExperiment):
"""Urukul Single Frequency ch1 for 2 sec"""
def build(self): #This code runs on the host device
self.setattr_device("core") #sets core device drivers as attributes
self.setattr_device("urukul0_ch1") #sets urukul0, channel 1 device drivers as attributes
@kernel
def run(self):
self.core.reset()
self.urukul0_ch1.cpld.init()
self.urukul0_ch1.init()
self.urukul0_ch1.cfg_sw(True)
# self.urukul0_ch1.set_att(6.*dB)
self.urukul0_ch1.set(10*MHz)
delay(2 * s)
self.urukul0_ch1.cfg_sw(False)
artiq_master/repository/Examples/Amplitude_Modulation/urukul_RAM_AM_scan.py
View file @ d0b09909
...@@ -156,7 +156,7 @@ class AD9910RAM(EnvExperiment): ...@@ -156,7 +156,7 @@ class AD9910RAM(EnvExperiment):
frec_vec += [frec] frec_vec += [frec]
# print(f"{round(time()-t0,1)} : {frec} | {am_freq}") # print(f"{round(time()-t0,1)} : {frec} | {am_freq}")
sleep(self.scan_time_step) # sleep(self.scan_time_step)
print("Real frequencies values used:") print("Real frequencies values used:")
...@@ -192,7 +192,7 @@ class AD9910RAM(EnvExperiment): ...@@ -192,7 +192,7 @@ class AD9910RAM(EnvExperiment):
self.u.cpld.set_profile(0) self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8) self.u.cpld.io_update.pulse_mu(8)
delay(1*ms) delay(100*ms)
#write to ram #write to ram
if self.data_len>100: if self.data_len>100:
......
artiq_master/repository/Examples/Amplitude_Modulation/urukul_RAM_working_test_01.py deleted 100644 → 0
View file @ abfeb9c8
from artiq.experiment import * #Imports everything from experiment library
from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source
RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP)
# This code demonstrates use of the urukul RAM.
# It produces a 5 MHz waveform with this shape:
#
# |-------\
# | \
# | \
# -----| \-----
class AD9910RAM(EnvExperiment):
'''urukul_RAM_working_test_01.py'''
def build(self): #this code runs on the host computer
self.setattr_device("core") #sets core device drivers as attributes
self.u = self.get_device("urukul0_ch1") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u
@kernel #this code runs on the FPGA
def run(self):
#produce data to be loaded to RAM
n = 10 #defines variable n for list length exponent
data = [0]*(1 << n) #declares list as 2^n integer values
for i in range(len(data)//2): #splits list into 2 halves and defines each separately
data[i] = i << (32 - (n - 1)) #first half ramps up to maximum amplitude in machine units
data[i + len(data)//2] = 0xffff << 16 #second half holds maximum amplitude
#reset core
self.core.reset() #resets core device
#initialise
self.u.cpld.init() #initialises CPLD
self.u.init() #initialises urukul channel
delay(1*ms) #1ms delay
#set ram profile
self.u.set_profile_ram( #sets profile in RAM to be used
start=0, end=0 + len(data) - 1, step=250, #start/end give addresses of ends of ram data, step gives step length
profile=0, mode=RAM_MODE_CONT_RAMPUP) #mode: bidirectional ramp
self.u.cpld.set_profile(0) #sets CPLD profile pins
self.u.cpld.io_update.pulse_mu(8) #I think this clocks all the CPLD registers so they take the values written to them
delay(1*ms) #1ms delay
#write to ram
self.u.write_ram(data) #writes data list to ram
delay(10*ms) #10ms delay
#write to cfr
self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF) #writes to CFR1 (control function register 1)
#enables ram, sets ram data as amplitude scale factor
self.u.sw.on()
#set urukuln parameters and turn channel on
self.u.set_frequency(5*MHz) #sets frequency
self.u.cpld.io_update.pulse_mu(8) #I think this clocks all the CPLD registers so they take the values written to them
# self.u.set_att(10*dB) #sets attenuation
#turns urukul channel on
# self.core.break_realtime() #moves timestamp forward to prevent underflow
delay(1*ms) #this can alse be achieved with a fixed delay
#self.u.sw.off() #this can alse be achieved with a fixed delay
# while True: #loops until manually broken
# delay(1*ms) #1ms delay
#
# with parallel: #runs indented code in parallel
# self.u.cpld.set_profile(0) #profile 0 tells CPLD to start ramping up
#
# delay(2*us) #2us delay
#
# with parallel: #runs indented code in parallel
# self.u.cpld.set_profile(1) #profile 1 tells CPLD to start ramping back down
artiq_master/repository/Examples/Amplitude_Modulation/urukul_RAM_working_test_02.py deleted 100644 → 0
View file @ abfeb9c8
from artiq.experiment import * #Imports everything from experiment library
from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source
RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP)
# This code demonstrates use of the urukul RAM.
# It produces a 50 MHz square waveform
class AD9910RAM(EnvExperiment):
'''urukul_RAM_working_test_02.py'''
def build(self): #this code runs on the host computer
self.setattr_device("core") #sets core device drivers as attributes
self.u = self.get_device("urukul0_ch1") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u
@kernel #this code runs on the FPGA
def run(self):
#produce data to be loaded to RAM
n = 10 #defines variable n for list length exponent
data = [0]*(1 << n) #declares list as 2^n integer values
for i in range(len(data)//2): #splits list into 2 halves and defines each separately
data[i] = 0 << (32 - (n - 1)) #first half ramps up to maximum amplitude in machine units
data[i + len(data)//2] = 0xffff << 16 #second half holds maximum amplitude
#reset core
self.core.reset()
#initialise
self.u.cpld.init()
self.u.init()
delay(1*ms)
#set ram profile
self.u.set_profile_ram(
start=0, end=0 + len(data) - 1, step=4,
profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8)
delay(1*ms)
#write to ram
self.u.write_ram(data)
delay(10*ms)
#write to cfr
self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF)
self.u.sw.on()
#set urukuln parameters and turn channel on
self.u.set_frequency(50*MHz)
self.u.cpld.io_update.pulse_mu(8)
# self.u.set_att(10*dB)
# self.core.break_realtime()
delay(1*ms)
#self.u.sw.off()
artiq_master/repository/Examples/Amplitude_Modulation/urukul_RAM_working_test_03.py deleted 100644 → 0
View file @ abfeb9c8
from artiq.experiment import * #Imports everything from experiment library
from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source
RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP)
# This code demonstrates use of the urukul RAM.
# It produces a 50 MHz square waveform attenuated
# Tries to set two profiles
class AD9910RAM(EnvExperiment):
'''urukul_RAM_working_test_03.py'''
def build(self): #this code runs on the host computer
self.setattr_device("core") #sets core device drivers as attributes
self.u = self.get_device("urukul0_ch1") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u
@kernel #this code runs on the FPGA
def run(self):
#produce data to be loaded to RAM
# n = 10
# data = [0]*(1 << n)
# for i in range(len(data)):
# # data[i] = i << 18
# data[n-i] = i << 23
# #data[i + len(data)//2] = 0xffff << 16 #second half holds maximum amplitude
data = [0]*512 + [1000<<23]*512
data2 = [0]*512 + [100<<23]*512
#reset core
self.core.reset()
#initialise
self.u.cpld.init()
self.u.init()
delay(1*ms)
#set ram profile 0 -----------------------------
self.u.set_profile_ram(
start=0, end=0 + len(data) - 1, step=1,
profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8)
delay(1*ms)
#write to ram
self.u.write_ram(data)
delay(10*ms)
self.core.break_realtime()
#set ram profile 1 -----------------------------
self.u.set_profile_ram(
start=1024, end=1024 + len(data2) - 1, step=1,
profile=1, mode=RAM_MODE_CONT_RAMPUP)
self.u.cpld.set_profile(1)
self.u.cpld.io_update.pulse_mu(8)
delay(1*ms)
#write to ram
self.u.write_ram(data2)
delay(40*ms)
# --------------------------
self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8)
delay(1*ms)
#write to cfr
self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF, internal_profile=0)
self.u.sw.on()
#set urukuln parameters and turn channel on
self.u.set_frequency(50*MHz)
self.u.cpld.io_update.pulse_mu(8)
# self.u.set_att(10*dB)
# self.core.break_realtime()
delay(1*ms)
#self.u.sw.off()
artiq_master/repository/Experiments/Spectrum/With_calibration/IR/IR_spectrum_withcalib_delaysfixed_TwoIRLasers.py
View file @ d0b09909
...@@ -111,16 +111,22 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -111,16 +111,22 @@ class IR_Scan_withcal_optimized(EnvExperiment):
self.setattr_argument("Heating", BooleanValue(1==0), "Experiment params") self.setattr_argument("Heating", BooleanValue(1==0), "Experiment params")
self.setattr_argument("Scan_type",
EnumerationValue(["Calibrated_scan", "Defined_scan"]),
"Scan params")
self.setattr_argument("Scanning_frequencies", Scannable(
default=CenterScan(210*MHz, 20*MHz, 0.1*MHz),
unit="MHz",
scale=MHz,
global_min = 1*MHz,
global_max = 400*MHz
),
"Scan params")
self.setattr_argument("Comments", StringValue(" "), "General comments") self.setattr_argument("Comments", StringValue(" "), "General comments")
#self.setattr_argument("UV_Freqs", Scannable(
# default=CenterScan(110*MHz, 10*MHz, 0.1*MHz),
# unit="MHz",
# scale=MHz,
# global_min = 1*MHz,
# global_max = 400*MHz
# )
# )
@rpc @rpc
def create_datasets(self): def create_datasets(self):
...@@ -169,8 +175,12 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -169,8 +175,12 @@ class IR_Scan_withcal_optimized(EnvExperiment):
self.ccb.issue("create_applet", "IR_espectro_fixeddelays", self.ccb.issue("create_applet", "IR_espectro_fixeddelays",
"${python} -m pyLIAF.artiq.applets.plot_xy " "${python} -m pyLIAF.artiq.applets.plot_xy "
"counts_spectrum " "counts_spectrum "
"--x Experiment_freqs_IR") "--x IR1_Frequencies")
self.ccb.issue("create_applet", "Scanning_amps",
"${python} -m pyLIAF.artiq.applets.plot_xy "
"IR1_Amplitudes "
"--x IR1_Frequencies")
@rpc @rpc
def Get_Calibrated_Frequencies(self) -> TList(TFloat): def Get_Calibrated_Frequencies(self) -> TList(TFloat):
...@@ -178,10 +188,16 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -178,10 +188,16 @@ class IR_Scan_withcal_optimized(EnvExperiment):
Calibrated_Experiment_freqs = self.get_dataset("Experiment_freqs_IR_fine") Calibrated_Experiment_freqs = self.get_dataset("Experiment_freqs_IR_fine")
else: else:
Calibrated_Experiment_freqs = self.get_dataset("Experiment_freqs_IR") Calibrated_Experiment_freqs = self.get_dataset("Experiment_freqs_IR")
self.set_dataset("IR1_Frequencies", np.array(Calibrated_Experiment_freqs), broadcast=True, archive=True) self.set_dataset("IR1_Frequencies_calibrated", np.array(Calibrated_Experiment_freqs), broadcast=True, archive=True)
if self.Scan_type == "Calibrated_scan":
Experiment_freqs = Calibrated_Experiment_freqs
elif self.Scan_type == "Defined_scan":
Experiment_freqs = self.Scanning_frequencies.sequence
self.set_dataset("IR1_Frequencies", np.array(Experiment_freqs), broadcast=True, archive=True)
self.set_dataset("no_freqs", len(Calibrated_Experiment_freqs), broadcast=True, archive=True) self.set_dataset("no_freqs", len(Calibrated_Experiment_freqs), broadcast=True, archive=True)
self.set_dataset("counts_spectrum", np.zeros(len(Calibrated_Experiment_freqs), dtype=int), broadcast=True, archive=True) self.set_dataset("counts_spectrum", np.zeros(len(Experiment_freqs), dtype=int), broadcast=True, archive=True)
return Calibrated_Experiment_freqs return Experiment_freqs
@rpc @rpc
...@@ -190,8 +206,23 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -190,8 +206,23 @@ class IR_Scan_withcal_optimized(EnvExperiment):
Calibrated_Experiment_amps = list(self.get_dataset("Experiment_amps_IR_fine")) Calibrated_Experiment_amps = list(self.get_dataset("Experiment_amps_IR_fine"))
else: else:
Calibrated_Experiment_amps = list(self.get_dataset("Experiment_amps_IR")) Calibrated_Experiment_amps = list(self.get_dataset("Experiment_amps_IR"))
self.set_dataset("IR1_Amplitudes", Calibrated_Experiment_amps, broadcast=True, archive=True) self.set_dataset("IR1_Amplitudes_calibrated", Calibrated_Experiment_amps, broadcast=True, archive=True)
return Calibrated_Experiment_amps
if self.Scan_type == "Calibrated_scan":
Experiment_amps = Calibrated_Experiment_amps
elif self.Scan_type == "Defined_scan":
Experiment_amps = []
Experiment_freqs = self.Scanning_frequencies.sequence
if self.Fine_scan:
Calibrated_Experiment_freqs = self.get_dataset("Experiment_freqs_IR_fine")
else:
Calibrated_Experiment_freqs = self.get_dataset("Experiment_freqs_IR")
for f in Experiment_freqs:
idx = (np.abs(np.asarray(Calibrated_Experiment_freqs) - f)).argmin() #busco el valor mas cercano en las freqs calibradas
Experiment_amps.append(Calibrated_Experiment_amps[idx])
self.set_dataset("IR1_Amplitudes", Experiment_amps, broadcast=True, archive=True)
return Experiment_amps
@kernel @kernel
...@@ -228,8 +259,11 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -228,8 +259,11 @@ class IR_Scan_withcal_optimized(EnvExperiment):
else: else:
delay(100*us) delay(100*us)
if self.Heating: if self.Heating:
self.calentar_ion() self.laserUV.off()
delay(self.t_heating) delay(self.t_heating)
self.laserUV.on()
#self.enfriar_ion()
#delay(0.001*self.t_heating)
cuentas = self.readout() # Hago la medicion y vuelvo con las cuentas cuentas = self.readout() # Hago la medicion y vuelvo con las cuentas
Accumulated_counts = Accumulated_counts + cuentas Accumulated_counts = Accumulated_counts + cuentas
self.mutate_dataset("counts_spectrum", iter_index, Accumulated_counts) self.mutate_dataset("counts_spectrum", iter_index, Accumulated_counts)
...@@ -257,7 +291,7 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -257,7 +291,7 @@ class IR_Scan_withcal_optimized(EnvExperiment):
#self.laserIR.initialize_channel() #self.laserIR.initialize_channel()
delay(1*ms) delay(1*ms)
# Seteo los perfiles 0 y 1 con los mismos valores # Seteo los perfiles 0 y 1 con los mismos valores
# el 0 va a ser el de ENFRIADO, el 1 va a ser el de MEDICION # el 0 va a ser el de ENFRIADO, el 1 va a ser el de MEDICION y el 2 va a ser de CALENTAMIENTO
self.laserIR1.set_channel() self.laserIR1.set_channel()
self.laserUV.set_channel() self.laserUV.set_channel()
self.laserIR2.set_channel() self.laserIR2.set_channel()
...@@ -282,9 +316,21 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -282,9 +316,21 @@ class IR_Scan_withcal_optimized(EnvExperiment):
self.laserIR2shift.set_frequency(270*MHz, 0.7, profile=1) self.laserIR2shift.set_frequency(270*MHz, 0.7, profile=1)
#self.laserTISA.set_frequency(self.TISA_CPT_freq, 0.035, profile=1) #self.laserTISA.set_frequency(self.TISA_CPT_freq, 0.035, profile=1)
self.core.break_realtime() self.core.break_realtime()
self.laserUV.set_channel(profile=2) #self.laserIR1.set_channel(profile=2)
self.core.break_realtime() #self.core.break_realtime()
self.laserUV.set_frequency(self.UV_CPT_freq, 0.0, profile=2) #self.laserUV.set_channel(profile=2)
#self.core.break_realtime()
#self.laserIR2.set_channel(profile=2)
#self.core.break_realtime()
#self.laserIR2shift.set_channel(profile=2)
#self.core.break_realtime()
#self.laserIR1.set_frequency(self.IR1_cooling_freq, self.IR1_cooling_amp, profile=2)
#self.core.break_realtime()
#self.laserIR2shift.set_frequency(270*MHz, 0.7, profile=2)
#self.core.break_realtime()
#self.laserUV.set_frequency(self.UV_cooling_freq, self.UV_cooling_amp, profile=2)
#self.core.break_realtime()
#self.laserIR2.set_frequency(self.IR2_cooling_freq, self.IR2_cooling_amp, profile=2)
# Me aseguro que todo termine antes de seguir # Me aseguro que todo termine antes de seguir
self.core.break_realtime() self.core.break_realtime()
...@@ -302,14 +348,16 @@ class IR_Scan_withcal_optimized(EnvExperiment): ...@@ -302,14 +348,16 @@ class IR_Scan_withcal_optimized(EnvExperiment):
@kernel @kernel
def calentar_ion(self): def calentar_ion(self):
"""Caliento el ion por un tiempo determinado apagando el laser UV""" """Caliento el ion por un tiempo determinado apagando el laser UV"""
self.laserUV.select_profile(2) self.laserUV.off()
@kernel @kernel
def readout(self) -> TInt64: def readout(self) -> TInt64:
"""Registro de cuentas emitidas""" """Registro de cuentas emitidas"""
self.laserUV.select_profile(1) # Paso al perfil que cambia self.laserUV.select_profile(1) # Paso al perfil que cambia
self.laserIR1.select_profile(1) # Paso al perfil que cambia self.laserIR1.select_profile(1) # Paso al perfil que cambia
self.laserIR2.select_profile(1) # Paso al perfil que cambia self.laserIR2.select_profile(1) # Paso al perfil que cambia
self.laserIR2shift.select_profile(1)
delay(self.t_trans) delay(self.t_trans)
here = self.pmt.gate_rising(self.t_readout) # Que mida durante t_readout here = self.pmt.gate_rising(self.t_readout) # Que mida durante t_readout
......
artiq_master/repository/Experiments/Spectrum/With_calibration/Motional/urukul_RAM_AM.py 0 → 100644
View file @ d0b09909
from artiq.experiment import * #Imports everything from experiment library
from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source
RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP)
from numpy import load,sin,linspace,pi,array
# This code demonstrates use of the urukul RAM.
# It produces a 50 MHz square waveform attenuated
FILENAME = "/home/liaf-ankylosaurus-admin/Documents/artiq/artiq_master/repository/Examples/Amplitude_Modulation/parametros_AM.npz"
dd = load(FILENAME)['dd']
def first(iterable, condition = lambda x: True , index=True):
"""
Returns the first item in the `iterable` that
satisfies the `condition`.
If the condition is not given, returns the first item of
the iterable.
Raises `StopIteration` if no item satysfing the condition is found.
>>> first( (1,2,3), condition=lambda x: x % 2 == 0)
2
>>> first(range(3, 100))
3
>>> first( () )
Traceback (most recent call last):
...
StopIteration
"""
if index:
return next( ii for ii,x in enumerate(iterable) if condition(x))
else:
return next(x for x in iterable if condition(x))
def get_urukul_params(f0: TFloat) -> list:
"""
get the array values for AM modulation in urukul for the frequency f0
params:
f0 (float): frequency to set on AM
"""
param = first(dd , lambda x: x[0]>=f0 , index=False)
frec, num_samples, clock_step, n_harmonic = param
xx = linspace(0, 2*pi*n_harmonic, num=num_samples, endpoint=False)
modulation = sin(xx)
return [frec, num_samples, clock_step, n_harmonic]
def get_urukul_array(frec: TInt32, num_samples: TInt32, n_harmonic: TInt32) -> list :
"""
get the array values for AM modulation in urukul for the frequency f0
params:
f0 (float): frequency to set on AM
"""
xx = linspace(0, 2*pi*n_harmonic, num=num_samples, endpoint=False)
modulation = sin(xx)
return modulation.tolist()
def convert_amp_to_data(amp):
"""
takes amp values (from 0 to 1) and returns data values (suitable for DDS load)
"""
MAX = 2**10-1
# N = 10
# if not iterable(amp):
# amp = [amp]
# return list([ int(round(val*MAX)) << 23 for val in amp ])
return list([ int(round(val*MAX)) for val in amp ])
class AD9910RAM(EnvExperiment):
'''Amplitude Modulation for Ch3'''
def build(self): #this code runs on the host computer
self.setattr_device("core") #sets core device drivers as attributes
self.u = self.get_device("urukul0_ch3") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u
# self.data=[0]*512 + [1000<<23]*512
self.data = [0]*1024
self.data_len = 1024
# GUI
self.frequency = self.get_argument(f"frequency",NumberValue(50*MHz, unit='MHz', scale=MHz, min=1*MHz, max=400*MHz),'ch3')
self.amplitude = self.get_argument(f"amplitude",NumberValue( 1, min=0.000, max=1.000),'ch3')
self.depth = self.get_argument(f"AM Depth", NumberValue( 0.1, min=0.000, max=1.000),'ch3')
self.am_freq = self.get_argument(f"AM frequency",NumberValue(100*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz),'ch3')
def run(self):
# print(self.am_freq)
# for am_delta in range(1000,5000,1000):
# parameters = get_urukul_params( self.am_freq + am_delta )
parameters = get_urukul_params( self.am_freq )
frec, num_samples, clock_step, n_harmonic = parameters
modulation = get_urukul_array(frec, num_samples, n_harmonic)
modulation = (array(modulation)/2 * self.depth ) + (self.amplitude-self.depth)
data = convert_amp_to_data( modulation )
self.clock_step = clock_step
self.data_len = len(data)
# entre 865 y 870
# self.data_len = 871
for ii in range(self.data_len):
self.data[ii] = data[ii]
# print(self.data)
print(f"frec: {frec} | am_freq: {self.am_freq} | num_samples:{num_samples} | clock_step: {clock_step}")
self.run_kernel()
@kernel #this code runs on the FPGA
def run_kernel(self):
data = [0] * self.data_len
for ii in range(self.data_len):
data[ii] = self.data[ii] << 23
self.core.break_realtime()
# modulation, frec, clock_step = get_urukul_array( self.am_freq )
# modulation = (modulation/2 * self.depth )+0.9
# data = convert_amp_to_data( modulation )
# data = [0]*512 + [1000<<23]*512
# clock_step = 1
#reset core
self.core.reset()
#initialise
self.u.cpld.init()
self.u.init()
delay(1*ms)
#set ram profile 0 -----------------------------
self.u.set_profile_ram(
start=0, end=0 + len(data) - 1, step=self.clock_step,
profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.u.cpld.set_profile(0)
self.u.cpld.io_update.pulse_mu(8)
delay(1*ms) # ES ESTE
#write to ram
self.u.write_ram(data)
#
#
# if self.data_len>100:
# self.u.set_profile_ram(
# start=0, end=0 + len(data[:100]) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms) # ES ESTE
# #write to ram
# self.u.write_ram(data[:100])
#
# delay(1*ms)
#
# self.u.set_profile_ram(
# start=len(data[:100]), end=len(data[:100]) + len(data[100:]) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms) # ES ESTE
# #write to ram
# self.u.write_ram(data[100:])
#
# delay(1*ms)
# self.u.set_profile_ram(
# start=0, end=0 + len(data[:100]) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
#
# else:
# self.u.set_profile_ram(
# start=0, end=0 + len(data) - 1, step=self.clock_step,
# profile=0, mode=RAM_MODE_CONT_RAMPUP)
#
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms) # ES ESTE
# #write to ram
# self.u.write_ram(data)
delay(10*ms)
self.core.break_realtime()
# --------------------------
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms)
#write to cfr
self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF, internal_profile=0)
self.u.sw.on()
#set urukuln parameters and turn channel on
self.u.set_frequency(self.frequency)
self.u.cpld.io_update.pulse_mu(8)
# self.u.set_att(10*dB)
# self.core.break_realtime()
delay(1*ms)
#self.u.sw.off()
artiq_master/repository/Experiments/Spectrum/With_calibration/Motional/urukul_RAM_AM_scan.py 0 → 100644
View file @ d0b09909
from artiq.experiment import * #Imports everything from experiment library
from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source
RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP)
from numpy import load,sin,linspace,pi,array
from time import sleep, time
# This code demonstrates use of the urukul RAM.
# It has a GUI for Artiq
FILENAME = "/home/liaf-ankylosaurus-admin/Documents/artiq/artiq_master/repository/Experiments/Spectrum/With_calibration/Motional/parametros_AM.npz"
dd = load(FILENAME)['dd']
def first(iterable, condition = lambda x: True , index=True):
"""
Returns the first item in the `iterable` that
satisfies the `condition`.
If the condition is not given, returns the first item of
the iterable.
Raises `StopIteration` if no item satysfing the condition is found.
>>> first( (1,2,3), condition=lambda x: x % 2 == 0)
2
>>> first(range(3, 100))
3
>>> first( () )
Traceback (most recent call last):
...
StopIteration
"""
if index:
return next( ii for ii,x in enumerate(iterable) if condition(x))
else:
return next(x for x in iterable if condition(x))
def get_urukul_params(f0: TFloat) -> list:
"""
get the array values for AM modulation in urukul for the frequency f0
params:
f0 (float): frequency to set on AM
"""
param = first(dd , lambda x: x[0]>=f0 , index=False)
frec, num_samples, clock_step, n_harmonic = param
xx = linspace(0, 2*pi*n_harmonic, num=num_samples, endpoint=False)
modulation = sin(xx)
return [frec, num_samples, clock_step, n_harmonic]
def get_urukul_array(frec: TInt32, num_samples: TInt32, n_harmonic: TInt32) -> list :
"""
get the array values for AM modulation in urukul for the frequency f0
params:
f0 (float): frequency to set on AM
"""
xx = linspace(0, 2*pi*n_harmonic, num=num_samples, endpoint=False)
modulation = sin(xx)
return modulation.tolist()
def convert_amp_to_data(amp):
"""
takes amp values (from 0 to 1) and returns data values (suitable for DDS load)
"""
MAX = 2**10-1
# N = 10
# if not iterable(amp):
# amp = [amp]
# return list([ int(round(val*MAX)) << 23 for val in amp ])
return list([ int(round(val*MAX)) for val in amp ])
class AD9910RAM(EnvExperiment):
'''Amplitude Modulation SCAN (multichannel)'''
def build(self): #this code runs on the host computer
self.setattr_device("core") #sets core device drivers as attributes
self.u0 = self.get_device("urukul0_ch0")
self.u1 = self.get_device("urukul0_ch1")
self.u2 = self.get_device("urukul0_ch2")
self.u3 = self.get_device("urukul0_ch3")
# self.data=[0]*512 + [1000<<23]*512
self.data = [0]*1024
self.data_len = 1024
# GUI
# self._channel_list = list( [ f'Ch{jj}' for jj in range(4) ] )
# self.channel = EnumerationValue(self._channel_list)
# self.setattr_argument("channel",EnumerationValue(self._channel_list))
self.frequency = self.get_argument(f"frequency" ,NumberValue( 208*MHz, unit='MHz', scale=MHz, min=1*MHz, max=400*MHz ))
self.amplitude = self.get_argument(f"amplitude" ,NumberValue( 0.25, min=0.000, max=1.000 ))
self.depth = self.get_argument(f"AM Depth" ,NumberValue( 0.15, min=0.000, max=1.000 ))
# self.am_freq = self.get_argument(f"AM frequency",NumberValue(100*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz),'ch1')
# GUI barrido
# self.am_freq_start = self.get_argument(f"AM frequency scan START",NumberValue(600*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz),'ch1')
# self.am_freq_end = self.get_argument(f"AM frequency scan END" ,NumberValue(800*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz),'ch1')
self.scan_time_step = self.get_argument(f"Scan time step" ,NumberValue(1 , min=0.01, max=60))
# self.scan_frec_step = self.get_argument(f"AM frequency step" ,NumberValue(1, unit='Hz', min=1 , max=1000000 ),'ch1')
self.sorted = self.get_argument(f"sorted", BooleanValue(1==0))
self.setattr_argument("freqs", Scannable(
default=CenterScan(700*kHz, 20*kHz, 1*kHz),
unit="kHz",
scale=kHz,
global_min = 1,
global_max = 1*MHz
)
)
def run(self):
# print(self.am_freq)
if self.sorted:
sequence = sorted(self.freqs.sequence)
else:
sequence = self.freqs.sequence
# self.ch_num = self._channel_list.index(self.channel)
print(f"Making SCAN from {sequence[0]/1000} kHz to {sequence[-1]/1000} on steps of {sequence[1]-sequence[0]} Hz.")
t0 = time()
frec_vec = []
for am_freq in sequence:
parameters = get_urukul_params( am_freq )
frec, num_samples, clock_step, n_harmonic = parameters
modulation = get_urukul_array(frec, num_samples, n_harmonic)
modulation = (array(modulation)/2 * self.depth ) + (self.amplitude-self.depth)
# modulation = ( (0.5+array(modulation)/2) * self.depth*self.amplitude ) + self.amplitude*(1-self.depth)
data = convert_amp_to_data( modulation )
self.clock_step = clock_step
self.data_len = len(data)
for ii in range(self.data_len):
self.data[ii] = data[ii]
# print(self.data)
print(f"{round(time()-t0,1)} : frec: {frec} | am_freq: {am_freq} | num_samples:{num_samples} | clock_step: {clock_step}")
self.run_kernel()
frec_vec += [frec]
# print(f"{round(time()-t0,1)} : {frec} | {am_freq}")
sleep(self.scan_time_step)
print("Real frequencies values used:")
print(frec_vec)
@kernel #this code runs on the FPGA
def run_kernel(self):
data = [0] * self.data_len
for ii in range(self.data_len):
data[ii] = self.data[ii] << 23
self.core.break_realtime()
# modulation, frec, clock_step = get_urukul_array( self.am_freq )
# modulation = (modulation/2 * self.depth )+0.9
# data = convert_amp_to_data( modulation )
# data = [0]*512 + [1000<<23]*512
# clock_step = 1
#reset core
self.core.reset()
#initialise
self.u3.cpld.init()
self.u3.init()
delay(1*ms)
#set ram profile 0 -----------------------------
self.u3.set_profile_ram(
start=0, end=0 + len(data) - 1, step=self.clock_step,
profile=0, mode=RAM_MODE_CONT_RAMPUP)
self.u3.cpld.set_profile(0)
self.u3.cpld.io_update.pulse_mu(8)
delay(1*ms)
#write to ram
self.u3.write_ram(data)
# if self.data_len>100:
# self.u3.write_ram(data[:100])
# self.u3.write_ram(data[100:])
# else:
# self.u3.write_ram(data)
delay(10*ms)
self.core.break_realtime()
# --------------------------
# self.u.cpld.set_profile(0)
# self.u.cpld.io_update.pulse_mu(8)
# delay(1*ms)
#write to cfr
self.u3.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF, internal_profile=0)
self.u3.sw.on()
#set urukuln parameters and turn channel on
self.u3.set_frequency(self.frequency)
self.u3.cpld.io_update.pulse_mu(8)
# self.u.set_att(10*dB)
# self.core.break_realtime()
delay(1*ms)
#self.u.sw.off()
artiq_master/repository/Examples/Amplitude_Modulation/urukul_RAM_AM_scan_BUG.py → artiq_master/repository/Experiments/Spectrum/With_calibration/Motional/urukul_RAM_AM_scan_ch3.py
View file @ d0b09909
...@@ -2,17 +2,15 @@ from artiq.experiment import * #Imp ...@@ -2,17 +2,15 @@ from artiq.experiment import * #Imp
from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source from artiq.coredevice.ad9910 import ( #Imports RAM destination amplitude scale factor and RAM mode bidirectional ramp methods from AD9910 Source
RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP) RAM_DEST_ASF, RAM_MODE_BIDIR_RAMP, RAM_MODE_CONT_RAMPUP)
import artiq
from numpy import load,sin,linspace,pi,array from numpy import load,sin,linspace,pi,array
from time import sleep, time from time import sleep, time
""" # This code demonstrates use of the urukul RAM.
This code is to REPRODUCE the BUG for AM modulation in try some solutions # It has a GUI for Artiq
"""
FILENAME = "/home/liaf-ankylosaurus-admin/Documents/artiq/artiq_master/repository/Examples/Amplitude_Modulation/parametros_AM.npz" FILENAME = "/home/liaf-ankylosaurus-admin/Documents/artiq/artiq_master/repository/Experiments/Spectrum/With_calibration/Motional/parametros_AM.npz"
dd = load(FILENAME)['dd'] dd = load(FILENAME)['dd']
...@@ -53,10 +51,8 @@ def get_urukul_params(f0: TFloat) -> list: ...@@ -53,10 +51,8 @@ def get_urukul_params(f0: TFloat) -> list:
f0 (float): frequency to set on AM f0 (float): frequency to set on AM
""" """
param = first(dd , lambda x: x[0]>=f0 , index=False) param = first(dd , lambda x: x[0]>=f0 , index=False)
frec, num_samples, clock_step, n_harmonic = param frec, num_samples, clock_step, n_harmonic = param
xx = linspace(0, 2*pi*n_harmonic, num=num_samples, endpoint=False) xx = linspace(0, 2*pi*n_harmonic, num=num_samples, endpoint=False)
modulation = sin(xx) modulation = sin(xx)
...@@ -95,20 +91,24 @@ def convert_amp_to_data(amp): ...@@ -95,20 +91,24 @@ def convert_amp_to_data(amp):
class AD9910RAM(EnvExperiment): class AD9910RAM(EnvExperiment):
'''Amplitude Modulation SCAN (BUG)''' '''Amplitude Modulation SCAN (ch3)'''
def build(self): #this code runs on the host computer def build(self): #this code runs on the host computer
self.setattr_device("core") #sets core device drivers as attributes self.setattr_device("core") #sets core device drivers as attributes
self.u = self.get_device("urukul0_ch1") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u self.u = self.get_device(f"urukul0_ch3") #sets urukul 0, channel 1 device drivers as attributes and renames object self.u
# self.data=[0]*512 + [1000<<23]*512 # self.data=[0]*512 + [1000<<23]*512
self.data = [0]*1024 self.data = [0]*1024
self.data_len = 1024 self.data_len = 1024
# GUI # GUI
self._channel_list = list( [ f'Ch{jj}' for jj in range(4) ] )
# self.channel = EnumerationValue(self._channel_list)
self.setattr_argument("channel",EnumerationValue(self._channel_list))
self.frequency = self.get_argument(f"frequency" ,NumberValue( 208*MHz, unit='MHz', scale=MHz, min=1*MHz, max=400*MHz )) self.frequency = self.get_argument(f"frequency" ,NumberValue( 208*MHz, unit='MHz', scale=MHz, min=1*MHz, max=400*MHz ))
self.amplitude = self.get_argument(f"amplitude" ,NumberValue( 0.25, min=0.000, max=1.000 )) self.amplitude = self.get_argument(f"amplitude" ,NumberValue( 0.25, min=0.000, max=1.000 ))
self.depth = self.get_argument(f"AM Depth" ,NumberValue( 0.15, min=0.000, max=1.000 )) self.depth = self.get_argument(f"AM Depth" ,NumberValue( 0.15, min=0.000, max=1.000 ))
# self.am_freq = self.get_argument(f"AM frequency",NumberValue(100*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz),'ch1') # self.am_freq = self.get_argument(f"AM frequency",NumberValue(100*kHz, unit='kHz', scale=kHz, min=100*kHz, max=2000*kHz),'ch1')
# GUI barrido # GUI barrido
...@@ -120,7 +120,7 @@ class AD9910RAM(EnvExperiment): ...@@ -120,7 +120,7 @@ class AD9910RAM(EnvExperiment):
self.sorted = self.get_argument(f"sorted", BooleanValue(1==0)) self.sorted = self.get_argument(f"sorted", BooleanValue(1==0))
self.setattr_argument("freqs", Scannable( self.setattr_argument("freqs", Scannable(
default=CenterScan(672*kHz, 2*kHz, 0.5*kHz), default=CenterScan(700*kHz, 20*kHz, 1*kHz),
unit="kHz", unit="kHz",
scale=kHz, scale=kHz,
global_min = 1, global_min = 1,
...@@ -128,18 +128,17 @@ class AD9910RAM(EnvExperiment): ...@@ -128,18 +128,17 @@ class AD9910RAM(EnvExperiment):
) )
) )
@rpc
def run(self): def run(self):
# print(self.am_freq) # print(self.am_freq)
self.kernel_init()
if self.sorted: if self.sorted:
sequence = sorted(self.freqs.sequence) sequence = sorted(self.freqs.sequence)
else: else:
sequence = self.freqs.sequence sequence = self.freqs.sequence
print(f"Making SCAN from {min(sequence)/1000} kHz to {max(sequence)/1000} on steps of {sequence[1]-sequence[0]} Hz.") # self.ch_num = self._channel_list.index(self.channel)
print(f"Making SCAN from {sequence[0]/1000} kHz to {sequence[-1]/1000} on steps of {sequence[1]-sequence[0]} Hz.")
t0 = time() t0 = time()
frec_vec = [] frec_vec = []
...@@ -147,7 +146,8 @@ class AD9910RAM(EnvExperiment): ...@@ -147,7 +146,8 @@ class AD9910RAM(EnvExperiment):
parameters = get_urukul_params( am_freq ) parameters = get_urukul_params( am_freq )
frec, num_samples, clock_step, n_harmonic = parameters frec, num_samples, clock_step, n_harmonic = parameters
modulation = get_urukul_array(frec, num_samples, n_harmonic) modulation = get_urukul_array(frec, num_samples, n_harmonic)
modulation = (array(modulation)/2 * self.depth ) + (self.amplitude-self.depth) # modulation = (array(modulation)/2 * self.depth ) + (self.amplitude-self.depth)
modulation = ( (0.5+array(modulation)/2) * self.depth*self.amplitude ) + self.amplitude*(1-self.depth)
data = convert_amp_to_data( modulation ) data = convert_amp_to_data( modulation )
self.clock_step = clock_step self.clock_step = clock_step
...@@ -169,37 +169,14 @@ class AD9910RAM(EnvExperiment): ...@@ -169,37 +169,14 @@ class AD9910RAM(EnvExperiment):
print("Real frequencies values used:") print("Real frequencies values used:")
print(frec_vec) print(frec_vec)
@kernel #this code runs on the FPGA
def kernel_init(self):
self.core.reset()
#initialise
self.u.cpld.init()
self.u.init()
delay(1*ms)
self.u.sw.on()
self.u.set_frequency(self.frequency)
self.u.cpld.io_update.pulse_mu(8)
self.core.break_realtime()
@kernel #this code runs on the FPGA @kernel #this code runs on the FPGA
def run_kernel(self): def run_kernel(self):
# self.core.break_realtime()
data = [0] * self.data_len data = [0] * self.data_len
for ii in range(self.data_len): for ii in range(self.data_len):
data[ii] = self.data[ii] << 23 data[ii] = self.data[ii] << 23
# delay(1*us)
delay(1*ms)
self.core.break_realtime()
# modulation, frec, clock_step = get_urukul_array( self.am_freq ) # modulation, frec, clock_step = get_urukul_array( self.am_freq )
# modulation = (modulation/2 * self.depth )+0.9 # modulation = (modulation/2 * self.depth )+0.9
...@@ -209,8 +186,8 @@ class AD9910RAM(EnvExperiment): ...@@ -209,8 +186,8 @@ class AD9910RAM(EnvExperiment):
#reset core #reset core
self.core.reset() self.core.reset()
#
# #initialise #initialise
self.u.cpld.init() self.u.cpld.init()
self.u.init() self.u.init()
delay(1*ms) delay(1*ms)
...@@ -225,27 +202,15 @@ class AD9910RAM(EnvExperiment): ...@@ -225,27 +202,15 @@ class AD9910RAM(EnvExperiment):
delay(1*ms) delay(1*ms)
#write to ram #write to ram
# try:
# self.u.write_ram(data)
# except RTIOUnderflow:
# # try again at the next mains cycle
# delay(10*ms)
# self.u.write_ram(data)
if self.data_len>100: if self.data_len>100:
self.u.write_ram(data[:100]) self.u.write_ram(data[:100])
self.u.write_ram(data[100:]) self.u.write_ram(data[100:])
else: else:
self.u.write_ram(data) self.u.write_ram(data)
# try:
# self.u.write_ram(data)
# except:
# print("ERROR on DATA LOADING")
delay(10*ms) delay(10*ms)
# self.core.break_realtime() self.core.break_realtime()
...@@ -258,12 +223,12 @@ class AD9910RAM(EnvExperiment): ...@@ -258,12 +223,12 @@ class AD9910RAM(EnvExperiment):
#write to cfr #write to cfr
self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF, internal_profile=0) self.u.set_cfr1(ram_enable=1, ram_destination=RAM_DEST_ASF, internal_profile=0)
# self.u.sw.on() self.u.sw.on()
# #set urukuln parameters and turn channel on #set urukuln parameters and turn channel on
# self.u.set_frequency(self.frequency) self.u.set_frequency(self.frequency)
self.u.cpld.io_update.pulse_mu(8) self.u.cpld.io_update.pulse_mu(8)
# self.u.set_att(10*dB) # self.u.set_att(10*dB)
self.core.break_realtime() # self.core.break_realtime()
delay(1*ms) delay(1*ms)
#self.u.sw.off() #self.u.sw.off()
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